a) Field Of the Invention
The present invention relates to computers and network processors in general and in particular to memory systems to be used with said computers and network processors.
b) Prior Art
The use of network devices such as switches, bridges, computers, network processors etc., for transferring information within communications network is well known in the prior art. One of the requirements placed on these devices is the need for them to transport large volumes of data often referred to as bandwidth.
To meet the high bandwidth requirement the devices are provided with Clear Channels. A Clear Channel is a channel with high bandwidth which transmits large amounts of data on a single flow, as opposed to channelized links which carry several lower bandwidth data flows on a single physical link.
In order to provide Clear Channels with ample supply of data, high speed storage subsystems are required. High speed storage systems such as Static Random Access Memories (SRAM) etc., can be used to meet high bandwidth requirements. But these memories are expensive and as a result increase the price of the devices in which they are used. The cost problem is further worsened if such high price memories were to be used to build storage systems for computers and Network Processors.
In addition to being expensive, the prior art high speed memories are low density. They can only store a limited amount of data. However, most applications especially those related to internet and other technologies require high density memories or storage systems. As a consequence even the prior art high speed memories are not suitable for many applications.
In view of the above there is a need for high speed memories that are low cost and have high densities. As used in this document high speed memories have large Bandwidth (BW) providing large amounts of data in a relatively short time interval. The invention described herein provides such a storage.
The invention includes methods that optimize utilization of a memory system by the resources using said memory system. In particular, the requests, read or write, from multiple requesters are bundled so that for each memory access cycle the maximum allowable unit of information is read or written. By so doing the information throughput is enhanced thereby allowing the use of relatively low cost, high density relatively slow access time memories, such as DDR DRAM, to be used to build storage for computer Network Processors or similar devices.
The requesters include the Receiver Controller, Embedded Processor Complex (EPC) Controller and Transmitter Controller in a Network Processor or like devices. The memory system includes a plurality of buffers, formed from DDR DRAM modules, which are arranged into groups termed xe2x80x9cslicesxe2x80x9d. Each DDR DRAM is partitioned into a plurality of buffers (1 through N) and is controlled by a DRAM controller. Each Buffer is partitioned into sections termed xe2x80x9cQuadwordsxe2x80x9d. In one embodiment the Buffer is partitioned in Quadwords A, B, C, D. Both the buffer and Quadwords in the buffer are addressable.
A memory arbiter monitors requests from the Receiver Controller, EPC Controller and Transmitter Controller. The memory arbiter uses the requests to form Memory Access Vector per slice of memory. For read requests, memory access priority is given to the Transmitter Controller. If the request from the Transmitter Controller requires full memory bandwidth, the Memory Access Vector is based upon the Transmitter Controller Request only. If less than full memory bandwidth is required, by the Transmitter Controller, any pending read requests by the EPC Controller is merged with that from the Transmitter Controller to form the memory access vector per slice. The DRAM Controller in response to the memory access vector output a full buffer of information containing data for the Transmitter Controller (if a full buffer of data has been requested) or data for the Transmitter Controller and EPC (if transmitter had requested less than full buffer). In essence any excess capacity, resulting from the Transmitter Controller requesting less than a full buffer of data, is allocated to the EPC Controller.
For Write Request, the Arbiter gives priority to the Receiver Controller. In a similar manner, any write requests in which the Receiver Controller has less than a full buffer payload is augmented with data from the EPC.
As a consequence a full buffer of data is always written or read on each memory access.